Maxim-integrated MAXQ7667 Manual de usuario descargar pdf (Pagina 289)

Bit 14: Burst Drive Strength (BDS). This bit selects the drive strength on the BURST pin. When the BDS bit is set to 0, the output dri-

ver is lower; when set to 1, the output driver is higher.

Bits 13 to 10: Reserved. Read returns 0.

Bits 9 to 0: Burst Pulse-Width High (BPH[9:0]). Defines the number of PLL clock cycles (BCKS = 0), or system clock cycles (BCKS

= 1) in each burst high pulse. When BPH is zero or one, the burst pulse-width high is 1 cycle. When BPH is equal to or greater than

the burst clock-cycle width, the burst pulse-width high is one cycle less than the clock cycle width (i.e., pulse-width low is one cycle).

17.3.2 Burst Transmit Control Register (BTRN)

Bits 15 to 12: Burst Clock-Divide Select (BDIV[3:0]).

Selects the divide ratio between the clock source specified by BCKS and the

burst and receive path clocks. Note that the receive path clock is not active for burst divide ratios of less than 160. Defaults to 1001

upon reset.

17-7 __________________________________________________________________________________________________________

MAXQ7667 User’s Guide

r = read, w = write

Note: BTRN is cleared to 9600h on all forms of reset.

Bit #

15 14 13 12 11 10 98

Name BDIV3 BDIV2 BDIV1 BDIV0 BPOL BCKS BTRI BGT

Reset 1 0 0 1 0 1 1 0

Access rw rw rw rw r w rw rw rw

Bit #

76543210

Name BCNT7 BCNT6 BCNT5 BCNT4 BCNT3 BCNT2 BCNT1 BCNT0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

PLL CLOCK CYCLES

BDIV

PER RECEIVE CLOCK CYCLE

(Rdivisor)

PER BURST CLOCK CYCLE

(Bdivisor)

0000 (0h) — 12

0001 (1h) — 16

0010 (2h) — 20

0011 (3h) — 28

0100 (4h) — 36

0101 (5h) — 48

0110 (6h) — 64

0111 (7h) — 90

1000 (8h) — 120

1001 (9h) 2 160

1010 (Ah) 3 240

1011 (Bh) 4 320

1100 (Ch) 5 400

1101 (Dh) 6 480

1110 (Eh) 7 560

1111 (Fh) 8 640

1 2 ... 284 285 286 287 288 289 290 291 292 293 294 ... 346 347

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Maxim-integrated MAXQ7667 Manual de usuario Pagina 289

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