11-3 __________________________________________________________________________________________________________
MAXQ7667 User’s Guide
11.2.1 TAP Pins
The TAP is formed by four interface signals as described in Table 11-1. The TAP signals are multiplexed with port pins P1.0, P1.1, P1.2,
and P1.3. These pins default to their JTAG TAP function on reset, which means that the MAXQ7667 device will always be ready for in-
circuit debugging or in-circuit programming following any reset.
Once an application has been loaded and starts running, the JTAG TAP port can still be used for in-circuit debugging operations. If
in-circuit debugging functionality is not needed, the P1.0, P1.1, P1.2, and P1.3 port pins can be reclaimed for application use by set-
ting the TAP (SC.7) bit to 0. This disables the JTAG TAP interface and allows the four pins to operate as normal port pins.
Table 11-1. MAXQ7667 TAP Pins
PIN
48
N A ME
MU L TIPLEXED WIT H
POR T SIGN A L
FUN CTION
46 TDO P1.0
JTAG Ser ial Test Data Output. This signal is used to serially transfer internal data to the
external host. Data is transferred least si gnificant bit fi rst. Data is dr iven out only on the falling
edge of TCK, only dur ing TAP Shift-IR or Shift-DR states and is otherw is e inactive. This pin is
weakly pulled high internal ly when inactive and/or when SC.7 (TAP) = 1. After power-up or a
reset this p in defaults to JTAG TDO pin.
47 TMS P1.1
JTAG Test Mode Select Input. This s ignal is sampled at the r is ing edge of TCK and controls
movement between TAP states . TMS is weakly pulled high internally when TAP = 1. After
power-up or a reset this pin defaults to JTAG TMS p in.
48 TDI P1.2
JTAG Ser ial Test Data Input. This signal is used to receive data serially transferred by the host.
Data is received least significant bit fi rst and is samp led on the r ising edge of TCK. TDI is
weakly pulled high internal ly when TAP = 1. After power -up or a reset this p in defaults to JTAG
TDI pin.
1 TCK P1.3
JTAG Ser ial Test Clock Input. Provided by the host. When this s ignal is stopped at 0, s torage
elements in the TAP logic retain thei r data indefinitely. TCK is weak ly pul led high internally
when TAP = 1. After power -up or a reset this p in defaults to JTAG TCK p in.
Figure 11-1. Simplified MAXQ7667 TAP and TAP Controller
P1.0/TDO
D
VDDIO
D
VDDIO
D
VDDIO
P1.2/TDI
W
RITE
P1.3/TCK
D
EBUG REGISTER
D
R-SCAN
SEQUENCE
U
PDATE-DR
UPDATE-DR
P1.1/TMS
SYSTEM PROGRAMMING REGISTER
READ
TO DEBUG
ENGINE
S
HADOW
R
EGISTER
POWER-ON
RESET
BYPASS
3
-BIT INSTRUCTION
S
HIFT REGISTER
7
6543210s1s0
210
210
D
VDDIO
IR-SCAN SEQUENCE
P
ARALLEL INSTRUCTION REGISTER
2
10
TAP CONTROLLER IR[2:0]
(114 paginas)
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