_________________________________________________________________________________________________________ 14-16
A D C D U AL -
MODE
(SA R D U L )
A D C CON VERSION
SOURCE
(SA RS [2:0])
A D C CON VERSION
TRIGGER
A D C CON VERSIO N DESCRIPTION
000 (Timer 0)
001 (Timer 1)
010 (Timer 2)
100 (ADCCTL)
Rising E dge of Conversion Source
• Sets T/H into track (acquis ition) mode.
• Track duration is under user control.
• If AD C is in auto shutdown, a m ini mum of 2.5µs (1µs for power -up and 1.5µs for
acquisit ion) is required.
• If AD C is not in auto shutdown, a m ini mum of 1.5µs acquisition delay is
required.
Falling E d ge of ADC CTL
• Sets T/H into hold (conversion) mode.
• Then SAR conversion executes (13 ADC clock cycles).
101
(Inverted AD C CTL)
Falling E d ge of ADC CTL
• Sets T/H into track mode.
• Track duration is under user control.
• If AD C is in auto shutdown, a m ini mum of 2.5µs (1µs for power -up and 1.5µs for
acquisit ion) is required.
• If AD C is not in auto shutdown, a m ini mum of 1.5µs acquisition delay is
required.
Rising E dge of ADC CTL
• Sets T/H into hold (conversion) mode.
• Then SAR conversion executes (13 ADC clock cycles ).
110
(C ontinuous )
Wr ite 110 to
SARS [2:0]
Wr ite 110 to SARS[2:0]
• If in auto shutdown, logic requires 8 cycles to power up.
• Sets T/H into track mode.
• ADC control logic provides the requi red track duration.
• T/H p laced in hold after 3 clock cycles.
• Then SAR conversion executes (13 ADC clock cycles ).
Conversion continuously repeated every 16 ADC clock cycles.
1
(D ual-E dge
Mode)
111
(Start/Busy Bit)
(This mode works
exactly as the s ingle-
edge mode.)
Wr ite 1 to SARBY
(Start/Busy Bit)
Wr ite 1 to SARBY (Start/Busy Bit)
• Sets T/H into track mode.
• ADC control logic provides the requi red track duration composed of power-up delay
(10 cycles ), acquisition delay (3 cycles), and settl ing delay.
• If AD C is in auto shutdown, T/H placed in hold after 11 clock cycles .
• If AD C is not in auto shutdown, T/H placed in hold i m med iately.
• Then SAR conversion executes (13 ADC clock cycles ).
000 (Timer 0)
001 (Timer 1)
010 (Timer 2)
100 (ADCCTL)
Falling E d ge of Conversion Source
• Sets T/H into track mode.
• ADC control logic provides the requi red track duration composed of power -up
delay (10 cycles ), acquis ition delay (3 cycles), and settl ing delay.
• If AD C is in auto shutdown, T/H placed in hold after 11 clock cycles .
• If AD C is not in auto shutdown, T/H placed in hold i mmed iately.
• Then SAR conversion executes (13 ADC clock cycles ).
0
(S ing le-E d ge
Mode)
101
(Inverted AD C CTL)
Rising E dge of ADC CTL
• Sets T/H into track mode.
• ADC control logic provides the requi red track duration composed of power -up
delay (10 cycles ), acquis ition delay (3 cycles), and settl ing delay.
• If AD C is in auto shutdown, T/H placed in hold after 11 clock cycles .
• If AD C is not in auto shutdown, T/H placed in hold i mmed iately.
• Then SAR conversion executes (13 ADC clock cycles).
(114 paginas)
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