Maxim-integrated DS4830 Optical Microcontroller Manual de usuario descargar pdf (Pagina 37)

DS4830 User’s Guide

Note: Some of the DS4830 module and peripheral interrupts sources are shown in the Figure 5-1 interrupt hierarchy

diagram. Please refer the corresponding sections of this user’s guide for more detailed information about all of the

possible interrupts.

5.1 – Servicing Interrupts

For the DS4830 to service an interrupt, interrupts must be enabled globally, modularly, and locally. The Interrupt Global

Enable (IGE) bit is located in the Interrupt Control (IC) register acts as a global interrupt mask. This bit defaults to 0, and it

must be set to 1 before any interrupt takes place.

The local interrupt-enable bit for a particular source is in one of the peripheral registers associated with that peripheral

module, or in a system register for any system interrupt source. Between the global and local enables are intermediate

per-module and system interrupt mask bits. These mask bits reside in the Interrupt Mask system register. By

implementing intermediate per-module masking capability in a single register, interrupt sources spanning multiple

modules can be selectively enabled/disabled in a single instruction. This promotes a simple, fast, and user-definable

interrupt prioritization scheme. The interrupt source-enable hierarchy is illustrated in Figure 5-1 as well as Table 5-1.

Table 5-1. Interrupt Sources and Control Bits

INTERRUPT

INTERRUPT FLAG

LOCAL ENABLE BIT

MODULE

INTERRUPT

IDENTIFICATIO

N BIT

INTERRUPT

IDENTIFICATION

BIT

MODULE

ENABLE

BIT

External Interrupt P2.0

EIF2.IE0

EIE2.EX0

IIR.II0

IMR.IM0

External Interrupt P2.1

EIF2.IE1

EIE2.EX1

External Interrupt P2.2

EIF2.IE2

EIE2.EX2

External Interrupt P2.3

EIF2.IE3

EIE2.EX3

External Interrupt P2.4

EIF2.IE4

EIE2.EX4

External Interrupt P2.5

EIF2.IE5

EIE2.EX5

External Interrupt P2.6

EIF2.IE6

EIE2.EX6

External Interrupt P2.7

EIF2.IE7

EIE2.EX7

External Interrupt P1.0

EIF1.IE0

EIE1.EX0

External Interrupt P1.1

EIF1.IE1

EIE1.EX1

External Interrupt P1.2

EIF1.IE2

EIE1.EX2

External Interrupt P1.3

EIF1.IE3

EIE1.EX3

External Interrupt P1.4

EIF1.IE4

EIE1.EX4

External Interrupt P1.5

EIF1.IE5

EIE1.EX5

External Interrupt P1.6

EIF1.IE6

EIE1.EX6

External Interrupt P1.7

EIF1.IE7

EIE1.EX7

External Interrupt P0.0

EIF0.IE0

EIE0.EX0

External Interrupt P0.1

EIF0.IE1

EIE0.EX1

External Interrupt P0.2

EIF0.IE2

EIE0.EX2

External Interrupt P0.3

EIF0.IE3

EIE0.EX3

External Interrupt P0.4

EIF0.IE4

EIE0.EX4

External Interrupt P0.5

EIF0.IE5

EIE0.EX5

External Interrupt P0.6

EIF0.IE6

EIE0.EX6

External Interrupt P0.7

EIF0.IE7

EIE0.EX7

Timer1 Interrupt

GTCN1.GTIF

GTCN1.GTIE

External Interrupt P6.0

EIF6.IE0

EIE6.EX0

MIIR1.P6_0

IIR.II1

IMR.IM1

External Interrupt P6.1

EIF6.IE1

EIE6.EX1

MIIR1.P6_1

External Interrupt P6.2

EIF6.IE2

EIE6.EX2

MIIR1.P6_2

External Interrupt P6.3

EIF6.IE3

EIE6.EX3

MIIR1.P6_3

External Interrupt P6.4

EIF6.IE4

EIE6.EX4

MIIR1.P6_4

External Interrupt P6.5

EIF6.IE5

EIE6.EX5

MIIR1.P6_5

External Interrupt P6.6

EIF6.IE6

EIE6.EX6

MIIR1.P6_6

Supply Voltage Monitor Interrupt

SVM.SVMI

SVM.SVMIE

MIIR1.SVM

C Master Start Interrupt

I2CST_M.I2CSRI

I2CIE_M.I2CSRIE

MIIR1.I2CM

C Master Transmit Complete Interrupt

I2CST_M.I2CTXI

I2CIE_M.I2CTXIE

C Master Receive Ready Interrupt

I2CST_M. I2CRXI

I2CIE_M.I2CRXIE

C Master Clock Stretch Interrupt

I2CST_M.I2CSTRI

I2CIE_M.I2CSTRIE

C Master Timeout Interrupt

I2CST_M.I2CTOI

I2CIE_M.I2CTOIE

C Master NACK Interrupt

I2CST_M.I2CNACKI

I2CIE_M.I2CNACKIE

C Master Receiver Overrun Interrupt

I2CST_M.I2CROI

I2CIE_M.I2CROIE

C Master Stop Interrupt

I2CST_M.I2CSPI

I2CIE_M.I2CSPIE

SPI Slave Transfer Complete

SPICN_S.SPIC

SPICF_S.ESPII

MIIR1.SPI_S

SPI Slave Write Collision

SPICN_S.WCOL

SPI Slave Receive Overrun

SPICN_S.ROVR

C Slave Stop Interrupt

I2CST_S.I2CSRI

I2CIE_S.I2CSRIE

MIIR2.I2CS

IIR.II2

IMR.IM2

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 226 227

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