
DS4830 User’s Guide
123
14.3.2.2 – Local Register PWMCGFn
PWMCN REG_SEL = 01b
PWMDATA[15:0] PWMCFGn[15:0]
Invert PWM Output. When this bit is set to ‘1’, PWM output is inverted for the selected
PWM channel (determined by the PWM_SEL[3:0] bits).
Reserved. The user should write 0 to this bit.
Alternate Location: PWM outputs at channels 0 to 7 are multiplexed with the DAC
outputs. By default, the PWM outputs appear at the DAC outputs. When ALT_LOC bit is
set to ‘1’, the PWM outputs will appear at the alternate location (See Table 14-3 for
details).
Local Enable: Setting this bit to ‘1’ will enable the individual PWM channel. PWM
operation will be enabled only when both local enable and the Master Enable M_EN in
PWMCN are enabled. Setting this bit to ‘0’ will disable the individual PWM channel.
Reserved. The user should not write to these bits.
Clock Select. These bits selects the PWM clock for selected PWM channel (which is
selected by PWM_SEL[3:0] bits).
The external clock range is 20MHz to 133MHz.
32-Slot Pulse Spreading: Setting this bit to ‘1’ enables 32-slot pulse spreading if PWM
resolution is 12 bits and PS4 bit is set to ‘1’. When this bit and PS4 are set to ‘1’, the PWM
period is divided into 32 slots of equal length. Setting this bit to ‘0’ disables the 32-slot
pulse spreading.
Reserved. The user should not write to these bits.
4-Slot Pulse Spreading: Setting this bit to ‘1’ enables 4-slot pulse spreading. When this
bit is set to ‘1’, the PWM period is divided into 4 slots of equal length. When this bit is set
to ‘0’, it disables 4-slot and 32-slot pulse spreading.
Reserved. The user should not write to this bit.
Resolution Select. These bits are used to configure PWM resolution (in bits) for selected
PWM channel (which is selected by PWM_SEL[3:0] bits). The PWM Frame frequency is
determined by the clock Frequency programmed and the resolution selected.
N
FrequencyClockPWM
FrequencyFramePWM
2
where n is the selected resolution.
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