
MAXQ Family User’s Guide:
MAXQ2010 Supplement
5-2
Table 5-2. Peripheral Register Bit Functions
REG
BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PO0 PO0 (8 bits)
PO1 PO1 (8 bits)
PO2 PO2 (8 bits)
PO3 PO3 (8 bits)
EIF0 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0
EIE0 EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0
PI0 PI0 (8 bits)
PI1 PI1 (8 bits)
PI2 PI2 (8 bits)
PI3 PI3 (8 bits)
EIES0 IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0
PWCN
FREQMD
— — — — —
X32KMD
(2 bits)
BOD
REGEN
X32K
BYP
HFXD
X32K
RDY
X32D FLOCK FLLEN
PD0 PD0 (8 bits)
PD1 PD1 (8 bits)
PD2 PD2 (8 bits)
PD3 PD3 (8 bits)
RTRM TSGN TRM (7 bits)
RCNT WE — ACS — — — FT SQE ALSF ALDF RDYE RDY BUSY ASE ADE RTCE
RTSS RTSS (8 bits)
RTSH RTSH (16 bits)
RTSL RTSL (16 bits)
RSSA RSSA (8 bits)
RASH — — — — RASH (4 bits)
RASL RASL (8 bits)
PO4 PO4 (8 bits)
PO5 — PO5 (7 bits)
PO6 PO6 (8 bits)
SPIB SPIB (16 bits)
EIF1 — IE14 IE13 IE12 IE11 IE10 IE9 IE8
EIE1 — EX14 EX13 EX12 EX11 EX10 EX9 EX8
EIF2 IE22 IE21 IE20 IE19 IE18 IE17 IE16 IE15
EIE2 EX22 EX21 EX20 EX19 EX18 EX17 EX16 EX15
PI4 PI4 (8 bits)
PI5 — PI5 (7 bits)
PI6 PI6 (8 bits)
EIES1 — IT14 IT13 IT12 IT11 IT10 IT9 IT8
EIES2 IT22 IT21 IT20 IT19 IT18 IT17 IT16 IT15
SVM — — — — SVTH (4 bits) — — —
SVM
STOP
SVMI SVMIE
SVM
RDY
SVMEN
PD4 PD4 (8 bits)
PD5 — PD5 (7 bits)
PD6 PD6 (8 bits)
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