Maxim-integrated DS4830A Optical Microcontroller Manual de usuario Pagina 41
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DS4830A User’s Guide
41
Note: Some of the DS4830A module and peripheral interrupts sources are shown in the Figure 5-1 interrupt
hierarchy diagram. See the corresponding sections of this user’s guide for more detailed information about all of the
possible interrupts.
5.1 – Servicing Interrupts
For the DS4830A to service an interrupt, interrupts must be enabled locally, modularly, and globally. The Interrupt
Global Enable (IGE) bit is located in the Interrupt Control (IC) register acts as a global interrupt mask. This bit
defaults to 0, and it must be set to 1 before any interrupt takes place.
The local interrupt-enable bit for a particular source is in one of the peripheral registers associated with that
peripheral module, or in a system register for any system interrupt source. Between the global and local enables are
intermediate per-module and system interrupt mask bits. These mask bits reside in the Interrupt Mask system
register. By implementing intermediate per-module masking capability in a single register, interrupt sources spanning
multiple modules can be selectively enabled/disabled in a single instruction. This promotes a simple, fast, and user-
definable interrupt prioritization scheme. The interrupt source-enable hierarchy is illustrated in Figure 5-1 as well as
Table 5-1.
Table 5-1: Interrupt Sources and Control Bits
INTERRUPT INTERRUPT FLAG LOCAL ENABLE BIT
MODULE
INTERRUPT
IDENTIFICATI
ON BIT
INTERRUPT
IDENTIFICATION
BIT
MODULE
ENABLE
BIT
External Interrupt Pp.n
(here p = 0,1,2 and n = 0 to 7)
EIFp.IEn EIEp.EXn -
IIR.II0 IMR.IM0
Timer1 Interrupt
GTCN1.GTIF
GTCN1.GTIE
-
External Interrupt Pp.n
(here p = 6 and n = 0 to 6)
EIFp.IEn EIEp.EXn MIIR1.Pp_n
IIR.II1 IMR.IM1
Supply Voltage Monitor Interrupt
SVM.SVMI
SVM.SVMIE
MIIR1.SVM
I
2
C Master Start Interrupt
I2CST_M.I2CSRI
I2CIE_M.I2CSRIE
MIIR1.I2CM
I
2
C Master Transmit Complete
Interrupt
I2CST_M.I2CTXI I2CIE_M.I2CTXIE
I
2
C Master Receive Ready Interrupt
I2CST_M. I2CRXI
I2CIE_M.I2CRXIE
I
2
C Master Clock Stretch Interrupt
I2CST_M.I2CSTRI
I2CIE_M.I2CSTRIE
I
2
C Master Timeout Interrupt
I2CST_M.I2CTOI
I2CIE_M.I2CTOIE
I
2
C Master NACK Interrupt
I2CST_M.I2CNACKI
I2CIE_M.I2CNACKIE
I
2
C Master Receiver Overrun Interrupt
I2CST_M.I2CROI
I2CIE_M.I2CROIE
I
2
C Master Stop Interrupt
I2CST_M.I2CSPI
I2CIE_M.I2CSPIE
I
2
C Slave Start Interrupt
I2CST_S.I2CSRI
I2CIE_S.I2CSRIE
- IIR.II2 IMR.IM2
I
2
C Slave Transmit Complete Interrupt
I2CST_S.I2CTXI
I2CIE_S.I2CTXIE
I
2
C Slave Receive Ready Interrupt
I2CST_S. I2CRXI
I2CIE_S.I2CRXIE
I
2
C Slave Clock Stretch Interrupt
I2CST_S.I2CSTRI
I2CIE_S.I2CSTRIE
I
2
C Slave Timeout Interrupt
I2CST_S.I2CTOI
I2CIE_S.I2CTOIE
I
2
C Slave Address Match Interrupt
I2CST_S.I2CAMI
I2CIE_S.I2CAMIE
I
2
C Slave NACK Interrupt
I2CST_S.I2CNACKI
I2CIE_S.I2CNACKIE
I
2
C Slave General Call Interrupt
I2ST_S.I2CGCI
I2CIE_S.I2CGCIE
I
2
C Slave Receiver Overrun Interrupt
I2CST_S.I2CROI
I2CIE_S.I2CROIE
I
2
C Slave Stop Interrupt
I2CST2_S.I2CSPI
I2CIE2_S.I2CSPIE
I
2
C Slave Start Address Interrupt
I2CST2_S.SADI
I2CIE2_S. SADIE
I
2
C Slave Memory Address Interrupt
I2CST2_S.MADI
I2CIE2_S. MADIE
I
2
C Slave Page Threshold Interrupt
I2CTXFST.THSH
I2CTXFIE.THSH
I
2
C Slave FIFO Threshold Interrupt
I2CRXFST.THSH
I2CRXFIE.THSH
Timer2 Interrupt
GTCN1.GTIF
GTCN1.GTIE
-
IIR.II3 IMR.IM3
Software Interrupts
SW.Fn
(n = 0,1,2,3)
- -
ADC Data Available Interrupt
ADST1.ADDAI
ADCN.ADDAIE
MIIR4.ADC
IIR.II4 IMR.IM4
Internal Temperature Interrupt
ADST1.INTDAI
TEMPCN.INT_IEN
Sample and Hold 0 Interrupt
ADST1.SH0DAI
SHCN.SHDAI0_EN
Sample and Hold 1 Interrupt ADST1.SH1DAI SHCN.SHDAI1_EN
3- Wire Interrupt
TWR.TWI
TWR.TWIE
MIIR4.TW
SPI Slave Transfer Complete
SPICN_S.SPIC
SPICF_S.ESPII
MIIR4.SPI_S
SPI Slave Write Collision
SPICN_S.WCOL
SPI Slave Receive Overrun
SPICN_S.ROVR
- DS4830A 1
- Optical Microcontroller 1
- User’s Guide 1
- Contents 2
- DS4830A User’s Guide 10
- SECTION 1 – OVERVIEW 11
- SECTION 2 – ARCHITECTURE 13
- 2.2 – Register Space 14
- 2.3 – Memory Types 15
- 2.5 – Data Alignment 22
- 2.6 – Reset Conditions 22
- 2.7 – Clock Generation 24
- INT_TRIG1 38
- INT_ALIGN 38
- BOOT_DIS 38
- SECTION 5 – INTERRUPTS 40
- 5.1 – Servicing Interrupts 41
- 6.1 – Detailed Description 45
- 6.3 – DAC Code Examples 47
- 7.1 – Detailed Description 48
- 7.3 – ADC Code Examples 63
- SECTION 8 – SAMPLE AND HOLD 65
- INT_TRIG_EN1 72
- INT_TRIG_EN0 72
- 9.1 – Detailed Description 73
- SECTION 10 – I 81
- 10.2 – I 90
- SECTION 11 – I 94
- C-COMPATIBLE SLAVE INTERFACE 94
- 11.1 – Detailed Description 95
- Detect START 96
- I2CSRI=1 96
- I2CBUS=1 96
- I2CBUSY=1 96
- 100 100
- 101 101
- 102 102
- 104 104
- 105 105
- 106 106
- 107 107
- 108 108
- 109 109
- 110 110
- SPI Slave 111
- 112 112
- 113 113
- 12.2 – SPI System Errors 113
- 114 114
- 115 115
- 116 116
- 117 117
- 118 118
- 119 119
- 120 120
- SECTION 13 – 3-WIRE 121
- 122 122
- 123 123
- Using PWMCN and 124
- 125 125
- 128 128
- 129 129
- 130 130
- 131 131
- 132 132
- 133 133
- 134 134
- FrequencyClockPWM 135
- FrequencyFrame 135
- 136 136
- 137 137
- 138 138
- 15.1 – Overview 138
- 140 140
- 141 141
- 142 142
- 143 143
- 16.1 – Detailed Description 143
- 144 144
- 145 145
- 146 146
- 147 147
- MULTIPLIER 148
- 149 149
- 150 150
- 151 151
- 152 152
- 153 153
- 154 154
- 155 155
- 156 156
- 19.1 - Overview 156
- 157 157
- 158 158
- 159 159
- 160 160
- 20.1 – TAP Controller 160
- 161 161
- 20.2 – TAP State Control 161
- 162 162
- 20.3 – Communication via TAP 162
- 163 163
- 164 164
- 165 165
- 166 166
- 167 167
- 168 168
- 169 169
- 170 170
- 21.2 – Debug Mode 170
- 171 171
- 172 172
- 173 173
- 174 174
- 175 175
- 176 176
- 177 177
- 178 178
- 179 179
- 22.1 – Detailed Description 179
- 180 180
- 181 181
- 182 182
- 22.2 – Bootloader Operation 182
- 183 183
- 184 184
- 22.3 – Bootloader Commands 184
- 185 185
- 186 186
- 187 187
- 188 188
- 189 189
- SECTION 23 – PROGRAMMING 190
- 191 191
- 192 192
- 193 193
- 194 194
- 195 195
- 196 196
- 197 197
- – Controlling Program Flow 197
- 198 198
- 199 199
- – Handling Interrupts 199
- 200 200
- – Accessing the Stack 200
- 201 201
- – Accessing Data Memory 201
- 202 202
- SECTION 24 – INSTRUCTION SET 203
- 204 204
- 205 205
- 206 206
- 207 207
- 208 208
- 209 209
- 210 210
- 211 211
- 212 212
- 213 213
- 214 214
- 215 215
- 216 216
- 217 217
- 218 218
- 219 219
- 220 220
- 221 221
- 222 222
- 223 223
- 224 224
- 225 225
- 226 226
- 227 227
- 228 228
- 229 229
- 230 230
- SECTION 25 – UTILITY ROM 231
- 232 232
- 233 233
- 234 234
- 235 235
- 236 236
- 237 237
- 25.4 Special Functions 237
- 238 238
- 25.5 – Utility ROM Examples 238
- SECTION 26 – MISCELLANEOUS 239
- 240 240
- 26.5 – Device Number and I 240
- C Bootloader Address Disable 240
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