Maxim-integrated DS4830A Optical Microcontroller Manual de usuario Pagina 203
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DS4830A User’s Guide
203
SECTION 24 – INSTRUCTION SET
Table 24-1. Instruction Set Summary
MNEMONIC DESCRIPTION
16-BIT INSTRUCTION
WORD
STATUS
BITS
AFFECTED
AP
INC/DEC
NOTES
LOGICAL OPERATIONS
AND src
Acc Acc AND src
f001 1010 ssss ssss
S, Z
Y
1
OR src
Acc Acc OR src
f010 1010 ssss ssss
S, Z
Y
1
XOR src
Acc Acc XOR src
f011 1010 ssss ssss
S, Z
Y
1
CPL
Acc ~Acc
1000 1010 0001 1010
S, Z
Y
NEG
Acc ~Acc + 1
1000 1010 1001 1010
S, Z
Y
SLA
Shift Acc left arithmetically
1000 1010 0010 1010
C, S, Z
Y
SLA2
Shift Acc left arithmetically twice
1000 1010 0011 1010
C, S, Z
Y
SLA4
Shift Acc left arithmetically four times
1000 1010 0110 1010
C, S, Z
Y
RL
Rotate Acc left (w/o C)
1000 1010 0100 1010
S
Y
RLC
Rotate Acc left (through C)
1000 1010 0101 1010
C, S, Z
Y
SRA
Shift Acc right arithmetically
1000 1010 1111 1010
C, Z
Y
SRA2
Shift Acc right arithmetically twice
1000 1010 1110 1010
C, Z
Y
SRA4
Shift Acc right arithmetically four times
1000 1010 1011 1010
C, Z
Y
SR
Shift Acc right (0 msbit)
1000 1010 1010 1010
C, S, Z
Y
RR
Rotate Acc right (w/o C)
1000 1010 1100 1010
S
Y
RRC
Rotate Acc right (though C)
1000 1010 1101 1010
C, S, Z
Y
BIT OPERATIONS
MOVE C, Acc.<b>
C
Acc.<b>
1110 1010 bbbb 1010
C
MOVE C, #0
C 0
1101 1010 0000 1010
C
MOVE C, #1
C 1
1101 1010 0001 1010
C
CPL C
C ~C
1101 1010 0010 1010
C
MOVE Acc.<b>, C
Acc.<b> C
1111 1010 bbbb 1010
S, Z
AND Acc.<b>
C C AND Acc.<b>
1001 1010 bbbb 1010
C
OR Acc.<b>
C C OR Acc.<b>
1010 1010 bbbb 1010
C
XOR Acc.<b>
C C XOR Acc.<b>
1011 1010 bbbb 1010
C
MOVE dst.<b>, #1
dst.<b> 1
1ddd dddd 1bbb 0111
C,E
2
MOVE dst.<b>, #0
dst.<b> 0
1ddd dddd 0bbb 0111
C,E
2
MOVE C, src.<b>
C
src.<b>
fbbb 0111 ssss ssss
C
MATH
ADD src
Acc Acc + src
f100 1010 ssss ssss
C, S, Z, OV
Y
1
ADDC src
Acc Acc + (src + C)
f110 1010 ssss ssss
C, S, Z, OV
Y
1
SUB src
Acc
Acc – src
f101 1010 ssss ssss
C, S, Z, OV
Y
1
SUBB src
Acc Acc – (src + C)
f111 1010 ssss ssss
C, S, Z, OV
Y
1
BRANCHING
{L/S}JUMP src
IP IP + src or src
f000 1100 ssss ssss
6
{L/S}JUMP C, src
If C=1, IP (IP + src) or src
f010 1100 ssss ssss
6
{L/S}JUMP NC, src
If C=0, IP (IP + src) or src
f110 1100 ssss ssss
6
{L/S}JUMP Z, src
If Z=1, IP (IP + src) or src
f001 1100 ssss ssss
6
{L/S}JUMP NZ, src
If Z=0, IP (IP + src) or src
f101 1100 ssss ssss
6
{L/S}JUMP E, src
If E=1, IP
(IP + src) or src
0011 1100 ssss ssss
6
{L/S}JUMP NE, src
If E=0, IP (IP + src) or src
0111 1100 ssss ssss
6
{L/S}JUMP S, src
If S=1, IP (IP + src) or src
f100 1100 ssss ssss
6
{L/S}DJNZ LC[n], src
If --LC[n] <> 0, IP
(IP + src) or src
f10n 1101 ssss ssss
6
{L/S}CALL src
@++SP IP+1; IP (IP+src) or src
f011 1101 ssss ssss
6,7
RET
IP @SP--
1000 1100 0000 1101
RET C
If C=1, IP @SP--
1010 1100 0000 1101
RET NC
If C=0, IP @SP--
1110 1100 0000 1101
RET Z
If Z=1, IP @SP--
1001 1100 0000 1101
RET NZ
If Z=0, IP @SP--
1101 1100 0000 1101
RET S
If S=1, IP @SP--
1100 1100 0000 1101
RETI
IP @SP-- ; INS 0
1000 1100 1000 1101
RETI C
If C=1, IP @SP-- ; INS 0
1010 1100 1000 1101
RETI NC
If C=0, IP
@SP-- ; INS
0
1110 1100 1000 1101
RETI Z
If Z=1, IP @SP-- ; INS 0
1001 1100 1000 1101
RETI NZ
If Z=0, IP @SP-- ; INS 0
1101 1100 1000 1101
RETI S
If S=1, IP @SP-- ; INS 0
1100 1100 1000 1101
DATA
TRANSFER
XCH
Swap Acc bytes
1000 1010 1000 1010
S
Y
XCHN
Swap nibbles in each Acc byte
1000 1010 0111 1010
S
Y
MOVE dst, src
dst src
fddd dddd ssss ssss
C,S,Z,E
(Note 8)
7,8
PUSH src
@++SP src
f000 1101 ssss ssss
7
POP dst
dst @SP--
1ddd dddd 0000 1101
C,S,Z,E
7
POPI dst
dst @SP-- ; INS 0
1ddd dddd 1000 1101
C,S,Z,E
7
CMP src
E
(Acc = src)
f111 1000 ssss ssss
E
NOP
No operation
1101 1010 0011 1010
Note 1: The active accumulator (Acc) is not allowed as the src in operations where it is the implicit destination.
Note 2: Only module 8 and modules 0-5 are supported by these single-cycle bit operations. Potentially affects C or E if PSF register is the
destination. Potentially affects S and/or Z if AP or APC is the destination.
Note 3: The terms Acc and A[AP] can be used interchangeably to denote the active accumulator.
- DS4830A 1
- Optical Microcontroller 1
- User’s Guide 1
- Contents 2
- DS4830A User’s Guide 10
- SECTION 1 – OVERVIEW 11
- SECTION 2 – ARCHITECTURE 13
- 2.2 – Register Space 14
- 2.3 – Memory Types 15
- 2.5 – Data Alignment 22
- 2.6 – Reset Conditions 22
- 2.7 – Clock Generation 24
- INT_TRIG1 38
- INT_ALIGN 38
- BOOT_DIS 38
- SECTION 5 – INTERRUPTS 40
- 5.1 – Servicing Interrupts 41
- 6.1 – Detailed Description 45
- 6.3 – DAC Code Examples 47
- 7.1 – Detailed Description 48
- 7.3 – ADC Code Examples 63
- SECTION 8 – SAMPLE AND HOLD 65
- INT_TRIG_EN1 72
- INT_TRIG_EN0 72
- 9.1 – Detailed Description 73
- SECTION 10 – I 81
- 10.2 – I 90
- SECTION 11 – I 94
- C-COMPATIBLE SLAVE INTERFACE 94
- 11.1 – Detailed Description 95
- Detect START 96
- I2CSRI=1 96
- I2CBUS=1 96
- I2CBUSY=1 96
- 100 100
- 101 101
- 102 102
- 104 104
- 105 105
- 106 106
- 107 107
- 108 108
- 109 109
- 110 110
- SPI Slave 111
- 112 112
- 113 113
- 12.2 – SPI System Errors 113
- 114 114
- 115 115
- 116 116
- 117 117
- 118 118
- 119 119
- 120 120
- SECTION 13 – 3-WIRE 121
- 122 122
- 123 123
- Using PWMCN and 124
- 125 125
- 128 128
- 129 129
- 130 130
- 131 131
- 132 132
- 133 133
- 134 134
- FrequencyClockPWM 135
- FrequencyFrame 135
- 136 136
- 137 137
- 138 138
- 15.1 – Overview 138
- 140 140
- 141 141
- 142 142
- 143 143
- 16.1 – Detailed Description 143
- 144 144
- 145 145
- 146 146
- 147 147
- MULTIPLIER 148
- 149 149
- 150 150
- 151 151
- 152 152
- 153 153
- 154 154
- 155 155
- 156 156
- 19.1 - Overview 156
- 157 157
- 158 158
- 159 159
- 160 160
- 20.1 – TAP Controller 160
- 161 161
- 20.2 – TAP State Control 161
- 162 162
- 20.3 – Communication via TAP 162
- 163 163
- 164 164
- 165 165
- 166 166
- 167 167
- 168 168
- 169 169
- 170 170
- 21.2 – Debug Mode 170
- 171 171
- 172 172
- 173 173
- 174 174
- 175 175
- 176 176
- 177 177
- 178 178
- 179 179
- 22.1 – Detailed Description 179
- 180 180
- 181 181
- 182 182
- 22.2 – Bootloader Operation 182
- 183 183
- 184 184
- 22.3 – Bootloader Commands 184
- 185 185
- 186 186
- 187 187
- 188 188
- 189 189
- SECTION 23 – PROGRAMMING 190
- 191 191
- 192 192
- 193 193
- 194 194
- 195 195
- 196 196
- 197 197
- – Controlling Program Flow 197
- 198 198
- 199 199
- – Handling Interrupts 199
- 200 200
- – Accessing the Stack 200
- 201 201
- – Accessing Data Memory 201
- 202 202
- SECTION 24 – INSTRUCTION SET 203
- 204 204
- 205 205
- 206 206
- 207 207
- 208 208
- 209 209
- 210 210
- 211 211
- 212 212
- 213 213
- 214 214
- 215 215
- 216 216
- 217 217
- 218 218
- 219 219
- 220 220
- 221 221
- 222 222
- 223 223
- 224 224
- 225 225
- 226 226
- 227 227
- 228 228
- 229 229
- 230 230
- SECTION 25 – UTILITY ROM 231
- 232 232
- 233 233
- 234 234
- 235 235
- 236 236
- 237 237
- 25.4 Special Functions 237
- 238 238
- 25.5 – Utility ROM Examples 238
- SECTION 26 – MISCELLANEOUS 239
- 240 240
- 26.5 – Device Number and I 240
- C Bootloader Address Disable 240
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