Maxim-integrated DS4830A Optical Microcontroller Manual de usuario descargar pdf (Pagina 132)

DS4830A User’s Guide

132

Programmed Delay. Max 8 Bits (256 clock cycles),

for 10 bits of Resolution & 4-slot pulse spreading

Source Clock

Figure 14-6: PWM Delay Operation without Pulse Spreading

14.2.3.1 – PWM DELAY with PWMSYNC SFR

The PWM channels to be synchronized must have the same configurations (Resolution, Pulse Spreading option, Clock

source etc.). The delays on the two channels can be different. After the synchronization, the programmed delay is

maintained as shown in Figure 14-7.

PWMSYNC = 00h PWMSYNC = 03h PWMSYNC = 00h

PWM1

PWM0

Core Clock

Figure 14-7: PWM Output Synchronization with 4 Clocks Delay

14.3 – PWM Output Register Descriptions

The DS4830A PWM controller has three SFRs. These are PWM Control Register PWMCN, PWM Data Register

PWMDATA and PWM Synchronization Register PWMSYNC. The PWMCN configures and controls the various PWM

operations. The PWMDATA register configures various PWM configurations and the PWMSYNC is used in PWM

synchronization operation. The PWMCN, PWMDATA and PWMSYNC registers are cleared on POR only.

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Maxim-integrated DS4830A Optical Microcontroller Manual de usuario Pagina 132