
Timer 2 Example: Triggering a Periodic Interrupt
move PD0, #0FFh ; Set P0.0-P0.7 to output mode
move PO0, #000h ; Drive low on all Port 0 pins
move IV, #IntHandler ; Set address for interrupt handler
move IMR.3, #1 ; Enable interrupts for module 3
move T2CFG0, #070h ; 16-bit timer mode, system clock / 128
move T2V0, #0CCCCh ; Period = (10000h-0CCCCh)*128 / Clock
move T2CNA0.3, #1 ; Start timer 0
move T2CNA0.7, #1 ; Enable timer 0 interrupts
move IC, #1 ; Enable global interrupts
jump $
IntHandler:
move T2CNB0, #00h ; Clear interrupt flags
move T2V0, #0CCCCh ; Reset for the same period
move Acc, PO0 ; Get current Port 0 output
cpl ; Toggle all bits
move PO0, Acc ; Set new Port 0 output
reti
MAXQ Family User’s Guide:
MAXQ2000 Supplement
REGISTER ADDRESS FUNCTION
T2V1 M4[09h]
Timer/Counter 1 (Type 2) Value Register
T2H1 M4[01h] Timer/Counter 1 (Type 2) Value MSB Register. Provides access to high byte of T2V.
T2R1 M4[0Ah]
Timer/Counter 1 (Type 2) Reload Register
T2RH1 M4[02h]
Timer/Counter 1 (Type 2) Reload MSB Register. Provides access to high byte of T2R.
T2C1 M4[0Bh]
Timer/Counter 1 (Type 2) Capture/Compare Register
T2CH1 M4[03h]
Timer/Counter 1 (Type 2) Capture/Compare MSB Register. Access to high byte of T2C.
T2CFG2 M4[11h]
Timer/Counter 2 (Type 2) Configuration Register. Controls counter/timer select, capture/compare function
select, 8-bit/16-bit mode select, and clock divide modes.
T2CNA2 M4[04h] Timer/Counter 2 (Type 2) Control Register A. I/O settings, run enables, polarity modes.
T2CNB2 M4[0Ch]
Timer/Counter 2 (Type 2) Control Register B. Contains capture, compare, overflow flags.
T2V2 M4[0Dh]
Timer/Counter 2 (Type 2) Value Register
T2H2 M4[05h]
Timer/Counter 2 (Type 2) Value MSB Register. Provides access to high byte of T2V.
T2R2 M4[0Eh]
Timer/Counter 2 (Type 2) Reload Register
T2RH2 M4[06h]
Timer/Counter 2 (Type 2) Reload MSB Register. Provides access to high byte of T2R.
T2C2 M4[0Fh]
Timer/Counter 2 (Type 2) Capture/Compare Register
T2CH2 M4[07h] Timer/Counter 2 (Type 2) Capture/Compare MSB Register. Access to high byte of T2C.
Table 14. Type 2 Timer/Counter Control Registers (continued)
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