
MAXQ Family User’s Guide:
MAXQ2000 Supplement
BIT15
BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 T2C0.9
SM0/FE
SM1 SM2 REN TB8 RB8 TI RI
SBUF1 (8 bits)
SMD1 —————ESI1
SMOD1
ET2L T2OE1 T2POL1 TR2L
TF2L TCC2
T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10 T2V0.9 T2V0.8 T2V0.7 T2V0.6 T2V0.5 T2V0.4 T2V0.3 T2V0.2 T2V0.1
T2R0.15 T2R0.14 T2R0.13 T2R0.12 T2R0.11 T2R0.10 T2R0.9 T2R0.8 T2R0.7 T2R0.6 T2R0.5 T2R0.4 T2R0.3 T2R0.2 T2R0.1
T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 T2C0.9 T2C0.8 T2C0.7 T2C0.6 T2C0.5 T2C0.4 T2C0.3 T2C0.2 T2C0.1
T2C1 DIV2
DIV0 T2MD CCF1 CCF0
C/T2
OWA — — — — — A2 A1 A0
OWD OWD (8 bits)
STBY SPIC ROVR WCOL MODF MODFE MSTM
ESPI1
CKPHA
CKR7 CKR6 CKR5 CKR4 CKR3 CKR2 CKR1
PSS1 PSS0
T2OE0 T2POL0 TR2L
CPRL2
T2V1.15 T2V1.14 T2V1.13 T2V1.12 T2V1.11 T2V1.10 T2V1.9
T2R1.15 T2R1.14 T2R1.13 T2R1.12 T2R1.11 T2R1.10 T2R1.9
T2C1.15 T2C1.14 T2C1.13 T2C1.12 T2C1.11 T2C1.10 T2C1.9
T2OE0 T2POL0 TR2L
CPRL2
T2V2.15 T2V2.14 T2V2.13 T2V2.12 T2V2.11 T2V2.10 T2V2.9
T2R2.15 T2R2.14 T2R2.13 T2R2.12 T2R2.11 T2R2.10 T2R2.9
T2C2.15 T2C2.14 T2C2.13 T2C2.12 T2C2.11 T2C2.10 T2C2.9
ET2L T2OE1 T2POL1 TR2L
TF2L TCC2
T2V1.15 T2V1.14 T2V1.13 T2V1.12 T2V1.11 T2V1.10 T2V1.9 T2V1.8 T2V1.7 T2V1.6 T2V1.5 T2V1.4 T2V1.3 T2V1.2 T2V1.1
T2R1.15 T2R1.14 T2R1.13 T2R1.12 T2R1.11 T2R1.10 T2R1.9 T2R1.8 T2R1.7 T2R1.6 T2R1.5 T2R1.4 T2R1.3 T2R1.2 T2R1.1
T2C1.15 T2C1.14 T2C1.13 T2C1.12 T2C1.11 T2C1.10 T2C1.9 T2C1.8 T2C1.7 T2C1.6 T2C1.5 T2C1.4 T2C1.3 T2C1.2 T2C1.1
ET2L T2OE1 T2POL1 TR2L
TF2L TCC2
T2V2.15 T2V2.14 T2V2.13 T2V2.12 T2V2.11 T2V2.10 T2V2.9 T2V2.8 T2V2.7 T2V2.6 T2V2.5 T2V2.4 T2V2.3 T2V2.2 T2V2.1
T2R2.15 T2R2.14 T2R2.13 T2R2.12 T2R2.11 T2R2.10 T2R2.9 T2R2.8 T2R2.7 T2R2.6 T2R2.5 T2R2.4 T2R2.3 T2R2.2 T2R2.1
T2C2.15 T2C2.14 T2C2.13 T2C2.12 T2C2.11 T2C2.10 T2C2.9 T2C2.8 T2C2.7 T2C2.6 T2C2.5 T2C2.4 T2C2.3 T2C2.2 T2C2.1
T2C1 DIV2
DIV0 T2MD CCF1 CCF0
Table 8. Peripheral Register Bit Functions (continued)
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