Maxim-integrated MAXQ622 Manual de usuario descargar pdf (Pagina 56)

MAXQ612/MAXQ622 User’s Guide

3-20 Maxim Integrated

the processor to the lost position prior to the interrupt. By using the watchdog reset function, the processor is restarted

from the beginning of the program and therefore placed into a known state.

The watchdog timeout selection is made using bits WD1 (WDCN.5) and WD0 (WDCN.4). The watchdog has four time-

out selections based on the system clock frequency as shown Figure 3-1. Because the timeout is a function of the

system clock, the actual timeout interval is dependent on both the crystal frequency and the system clock mode selec-

tion. Table 3-3 shows a summary of the selectable watchdog timeout intervals for the various system clock modes and

WD[1:0] control bit settings. If enabled, the watchdog reset is always scheduled to occur 512 system clocks following

the timeout. Watchdog-generated resets last for eight system clock cycles.

Table 3-3. Watchdog Timeout Period Selection

SYSTEM CLOCK

MODE

SYSTEM CLOCK SELECT BITS

WATCHDOG TIMEOUT

(IN NUMBER OF OSCILLATOR CLOCKS)

PMME CD1 CD0 WD[1:0] = 00b WD[1:0] = 01b WD[1:0] = 10b WD[1:0] = 11b

Divide by 1 (default) 0 0 0 2

Divide by 2 0 0 1 2

Divide by 4 0 1 0 2

Divide by 8 0 1 1 2

Power-Management

Mode (Divide by 256)

1 x x 2

1 2 ... 51 52 53 54 55 56 57 58 59 60 61 ... 254 255

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Maxim-integrated MAXQ622 Manual de usuario Pagina 56