Maxim-integrated DS80C390 Manual de usuario

Busca en linea o descarga Manual de usuario para Hardware Maxim-integrated DS80C390. Maxim Integrated DS80C390 User Manual Manual de usuario

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FEATURES
§ 80C52 compatible
8051 instruction-set compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
§ High-Speed Architecture
4 clocks/machine cycle (8051=12)
Runs DC to 40 MHz clock rates
Frequency multiplier reduces EMI
Single-cycle instruction in 100 ns
16/32-bit math coprocessor
§ 4 kB internal SRAM usable as
program/data/stack memory
§ Enhanced memory architecture
Addresses up to 4 MB external
Defaults to true 8051 memory compatibility
User-enabled 22-bit program/data counter
16-Bit/22-bit paged/22-bit contiguous
modes
User-selectable multiplexed / non-
multiplexed memory interface
Optional 10 bit stack pointer
§ Two full-function CAN 2.0B controllers
15 message centers per controller
Standard 11-bit or extended 29-bit
identification modes
Supports DeviceNet, SDS, and higher layer
CAN protocols
Disables transmitter during autobaud
SIESTA low power mode
§ Two full-duplex hardware serial ports
§ Programmable IrDA clock
§ High integration controller includes
Power-fail reset
Early-warning power-fail interrupt
Programmable watchdog timer
Oscillator-fail detection
§ 16 total interrupt sources with 6 external
§ Available in 64-pin QFP, 68-pin PLCC
PIN ASSIGNMENT
DS80C390
Dual CAN High-Speed
Microprocessor
www.dalsemi.com
64-PIN QFP
PRELIMINARY
1
61
9
10
26
27
43
60
44
DS80C390
68-PIN PLCC
49
DS80C390
48 33
32
17
161
64
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Indice de contenidos

Pagina 1 - Microprocessor

1 of 58 110199FEATURES§ 80C52 compatible− 8051 instruction-set compatible− Four 8-bit I/O ports− Three 16-bit timer/counters− 256 bytes scratchp

Pagina 2 - ORDERING INFORMATION

DS80C39010 of 58 110199EIE CANBIE C0IE C1IE EWDI EX5 EX4 EX3 EX2 E8hMXAX EAhC1M1C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EBhC1M2C MSRDY ETI ERI I

Pagina 3 - 3 of 58 110199

DS80C39011 of 58 110199ARITHMETIC ACCELERATOR SEQUENCINGDivide (32/16 or 16/16) Multiply (16x16)Load MA with dividend LSB.Load MA with dividendLSB+1*L

Pagina 4 - PIN DESCRIPTION Table 1

DS80C39012 of 58 110199MEMORY ADDRESSINGThe DS80C390 incorporates three internal memory areas:§ 256 bytes of scratchpad (or direct) RAM§ 4 KB of SRA

Pagina 5 - INT1 External Interrupt 1

DS80C39013 of 58 110199INTERNAL MOVX SRAMThe DS80C390 contains 4kB of SRAM that can be configured as user accessible MOVX memory,program memory, or op

Pagina 6

DS80C39014 of 58 110199PROGRAM MEMORY CHIP ENABLE BOUNDARIES Table 7P4CNT.5-3CE0 CE1 CE2 CE3000 0h-7FFFh 8000h-FFFFh 10000h-17FFFh 18000h-1FFFFh100 0h

Pagina 7 - INSTRUCTION SET SUMMARY

DS80C39015 of 58 110199The reset default of one Stretch cycle results in a three cycle MOVX for any external access. Therefore,the default off-chip R

Pagina 8 - SPECIAL FUNCTION REGISTERS

DS80C39016 of 58 110199ENHANCED DUAL DATA POINTERSThe DS80C390 contains two data pointers, DPTR0 and DPTR1, designed to improve performance inapplicat

Pagina 9 - 9 of 58 110199

DS80C39017 of 58 11019980C32 Idle and power down (Stop) modes, the DS80C390 provides a new Power Management Mode.This mode allows the processor to con

Pagina 10

DS80C39018 of 58 110199SYSTEM CLOCK CONFIGURATION Table 10CD1 CD02X4X/Name Clocks/MC Max. External Frequency0 0 0 Frequency Multiplier (2X) 2 20 MHz0

Pagina 11 - 40-BIT ACCUMULATOR

DS80C39019 of 58 110199POWER MANAGEMENT MODE (PMM)Machine Cycle Rate Operating Current EstimatesCrystal SpeedFull Operation(4 clocks permachine cycle)

Pagina 12 - MEMORY ADDRESSING

DS80C3902 of 58 110199DESCRIPTIONThe DS80C390 is a fast 8051-compatible microprocessor. The redesigned processor core executes 8051instructions up to

Pagina 13 - EXTERNAL MEMORY ADDRESSING

DS80C39020 of 58 110199Software should not rely on a lower-priority level interrupt source to remove PMM (Switchback) when ahigher level is in service

Pagina 14 - STRETCH MEMORY CYCLES

DS80C39021 of 58 110199During Stop mode the crystal oscillator is halted to maximize power savings. Typically 4 - 10 ms arerequired for an external c

Pagina 15 - EXTENDED STACK POINTER

DS80C39022 of 58 110199EMI REDUCTIONOne of the major contributors to radiated noise in an 8051-based system is the toggling of ALE. Themicrocontrolle

Pagina 16 - ENHANCED DUAL DATA POINTERS

DS80C39023 of 58 110199during the debug process to determine where watchdog reset commands must be located in theapplication software. The interrupt

Pagina 17 - SYSTEM CLOCK CONTROL

DS80C39024 of 58 110199EXTERNAL RESET PINSThe DS80C390 has both reset input (RST) and reset output (RSTOL ) pins. The RSTOL pin supplies anactive l

Pagina 18 - OSCILLATOR FAIL DETECT

DS80C39025 of 58 110199CONTROLLER AREA NETWORK (CAN) MODULEThe DS80C390 incorporates two CAN controllers that are fully compliant with the CAN 2.0Bspe

Pagina 19 - SWITCHBACK

DS80C39026 of 58 110199Each of the message centers is identical with the exception of message center 15. Message center 15 hasbeen designed as a rece

Pagina 20 - RING OSCILLATOR

DS80C39027 of 58 110199CAN 0 MESSAGE CENTERS 2-14MESSAGE CENTER 2 REGISTERS (similar to Message Center 1) xxxx20h - 2FhMESSAGE CENTER 3 REGISTERS (sim

Pagina 21 - TIMED ACCESS PROTECTION

DS80C39028 of 58 110199MOVX MESSAGE CENTERS FOR CAN 1CAN 1 CONTROL/STATUS/MASK REGISTERSRegister 7 6 5 4 3 2 1 0MOVX DataAddress1C1MID0 MID07 MID06 MI

Pagina 22 - WATCHDOG TIMER

DS80C39029 of 58 110199CAN 1 MESSAGE CENTER 15- Reserved xxxxF0h - F1hC1M15AR0 CAN 1 MESSAGE 15 ARBITRATION REGISTER 0 xxxxF2hC1M15AR1 CAN 1 MESSAGE 1

Pagina 23

DS80C3903 of 58 110199DS80C390 BLOCK DIAGRAM Figure 1

Pagina 24 - INTERRUPT SUMMARY Table 12

DS80C39030 of 58 110199compared directly or via a mask register. A special set of arbitration registers dedicated to Messagecenter 15 allow added fle

Pagina 25

DS80C39031 of 58 110199If the WTOE bit is set, the incoming message will be received and written over the existing data bytes inthat message center.

Pagina 26

DS80C39032 of 58 110199ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3 V to (VCC + 0.5 V)Voltage on VCC relative to ground -0.3 V

Pagina 27

DS80C39033 of 58 110199NOTES FOR DC ELECTRICAL CHARACTERISTICS:1. Active current measured with 40 MHz clock source on XTAL1, VCC=RST= 5.5 V, all othe

Pagina 28 - Register 7 6 5 4 3 2 1 0

DS80C39034 of 58 110199AC ELECTRICAL CHARACTERISTICS (Multiplexed address/data bus)40 MHz VARIABLE CLOCKPARAMETER SYMBOL MIN MAX MIN MAX UNITSOscillat

Pagina 29 - ARBITRATION AND MASKING

DS80C39035 of 58 110199MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLEMOVX CHARACTERISTICS (Multiplexed address/data bus)PARAMETER SYMBOL MIN MAX UNITS

Pagina 30 - MESSAGE BUFFERING/OVERWRITE

DS80C39036 of 58 110199tAVDV10.75 tMCS -20 ns CST = 0(CST+0.375)•tMCS -20 1≤ CST ≤ 3Port 0 Address, Port 4 CE,Port 5 PCE to Valid Data In(CST+1.375)•t

Pagina 31 - BIT TIMING

DS80C39037 of 58 110199ggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggggg

Pagina 32 - DC ELECTRICAL CHARACTERISTICS

DS80C39038 of 58 110199llllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllooooooooooooooooooooooooooooooooooooooooook

Pagina 33 - VERSUS FREQUENCY

DS80C39039 of 58 110199MULTIPLEXED 2 CYCLE DATA MEMORY 3-PCE0 READ OR WRITEMULTIPLEXED 2 CYCLE DATA MEMORY 3-CE0 READ

Pagina 34 - 4CE0 − Valid to ALE Low

DS80C3904 of 58 110199PIN DESCRIPTION Table 1LQFP PLCC SIGNALNAMEDESCRIPTION8, 22,40, 5617, 32,51, 68VCC+5V9, 25,41, 571, 18,35, 52GND Digital Circuit

Pagina 35 - 4CE0 − , 4PCE0− Valid to

DS80C39040 of 58 110199MULTIPLEXED 2 CYCLE DATA MEMORY 3-CE0 WRITEMULTIPLEXED 3 CYCLE DATA MEMORY 3-PCE0 READ OR WRITE

Pagina 36 - TIME PERIODS

DS80C39041 of 58 110199MULTIPLEXED 3 CYCLE DATA MEMORY 3-CE0 READMULTIPLEXED 3 CYCLE DATA MEMORY 3-CE0 WRITE

Pagina 37 - 37 of 58 110199

DS80C39042 of 58 110199MULTIPLEXED 9 CYCLE DATA MEMORY 3-PCE0 READ OR WRITEMULTIPLEXED 9 CYCLE DATA MEMORY 3-CE0 READ

Pagina 38 - 38 of 58 110199

DS80C39043 of 58 110199MULTIPLEXED 9 CYCLE DATA MEMORY 3-CE0 WRITEELECTRICAL CHARACTERISTICS (Non-multiplexed address/data bus)40 MHz VARIABLE CLOCK

Pagina 39 - 3-CE0 READ

DS80C39044 of 58 110199NON-MULTIPLEXED EXTERNAL PROGRAM MEMORY READ CYCLE

Pagina 40 - 3-CE0 WRITE

DS80C39045 of 58 110199MOVX CHARACTERISTICS (Non-multiplexed address/data bus)PARAMETER SYMBOL MIN MAX UNITS STRETCHVALUESCST (MD2:0)tPXIZ0.5 tMCS -5

Pagina 41

DS80C39046 of 58 110199Cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccl

Pagina 42

DS80C39047 of 58 110199cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc

Pagina 43

DS80C39048 of 58 110199NON-MULTIPLEXED 2 CYCLE DATA MEMORY 3-PCE0 READ OR WRITENON-MULTIPLEXED 2 CYCLE DATA MEMORY 3-CE0 READ

Pagina 44 - 44 of 58 110199

DS80C39049 of 58 110199NON-MULTIPLEXED 2 CYCLE DATA MEMORY 3-CE0 WRITENON-MULTIPLEXED 3 CYCLE DATA MEMORY 3-PCE0 READ OR WRITE

Pagina 45 - RD or WR

DS80C3905 of 58 11019958-64,12-8, 10 P1.0-P1.7 Port 1 - I/O. Port 1 can function as an 8-bit bi-directional I/O port,the non-multiplexed A0 - A7 sign

Pagina 46 - 46 of 58 110199

DS80C39050 of 58 110199NON-MULTIPLEXED 3 CYCLE DATA MEMORY 3-CE0 READNON-MULTIPLEXED 3 CYCLE DATA MEMORY 3-CE0 WRITE

Pagina 47 - 47 of 58 110199

DS80C39051 of 58 110199NON-MULTIPLEXED 9 CYCLE DATA MEMORY 3-PCE0 READ OR WRITENON-MULTIPLEXED 9 CYCLE DATA MEMORY 3-CE0 READ

Pagina 48

DS80C39052 of 58 110199NON-MULTIPLEXED 9 CYCLE DATA MEMORY 3-CE0 WRITEtMCS TIME PERIODSSystem Clock Selection2X4X/CD1 CD0 tMCS1 0 0 1 tCLCL0 0 0 2 t

Pagina 49

DS80C39053 of 58 110199SERIAL PORT MODE 0 TIMING CHARACTERISTICSPARAMETER SYMBOL TYPICAL UNITSSerial port clock cycle timeSM2=0:2 clocks per cycleSM2=

Pagina 50

DS80C39054 of 58 110199SERIAL PORT 0 (SYNCHRONOUS MODE)TRADITIONAL 8051 OPERATION, TXD CLOCK=XTAL/12 (SM2=0)HIGH-SPEED OPERATION, TXD CLK = XTAL/4 (SM

Pagina 51

DS80C39055 of 58 110199EXPLANATION OF AC SYMBOLSThis microcontroller uses timing parameters and symbols similar to the original 8051 family. Thefollo

Pagina 52

DS80C39056 of 58 11019968-PIN PLCC

Pagina 53

DS80C39057 of 58 11019964-PIN LQFP

Pagina 54 - 54 of 58 110199

DS80C39058 of 58 110199DATA SHEET REVISION SUMMARYThe following represent the key differences between the 092499 and the 101999 version of theDS80C390

Pagina 55 - WR signal

DS80C3906 of 58 11019913 22P3.7 RD External Data Memory Read Strobe34-27 45, 44,42-37P4.0-P4.7 Port 4 - I/O. Port 4 can function as an 8-bit bi-dire

Pagina 56 - 68-PIN PLCC

DS80C3907 of 58 11019980C32 COMPATIBILITYThe DS80C390 is a CMOS 80C32-compatible microcontroller designed for high performance. Everyeffort has been

Pagina 57 - 64-PIN LQFP

DS80C3908 of 58 110199required the same amount of time: two machine cycles or 24 oscillator cycles. In the DS80C390, theMOVX instruction takes as lit

Pagina 58 - DATA SHEET REVISION SUMMARY

DS80C3909 of 58 110199C0IR INTIN7 INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0 A5hC0TE A6hC0RE A7hIE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8hSADDR0 A9hS

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