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Maxim Integrated 2-3

MAX31782 User’s Guide

Revision 0; 8/11

This instruction word format presents the following limitations.

1) There are 32 registers per register module, but only 4 bits are allocated to designate the source register and only 3

bits are allocated to designate the destination register.

2) The source field only provides 8 bits of data for an immediate value; however, a 16-bit immediate value can be

required.

The MAX31782 uses a prefix register (PFX) to address these limitations. The PFX register provides the additional bits

required to access all 32 registers within a module. The PFX register also provides the additional 8 bits of data required

to make a 16-bit immediate data source. The data that is written to the PFX register survives for only one clock cycle.

This means the write to the PFX register must occur immediately prior to the instruction requiring the PFX register. The

PFX register is cleared to zero after one cycle so it does not affect any other instructions. The write to the PFX register is

done automatically by the assembler and requires one additional execution cycle. So, while most instructions execute

in a single cycle, two cycles are needed for instructions that require the PFX register.

The architecture of the MAX31782 is transport-triggered. This means that writing to or reading from certain register

locations also causes side effects to occur. These side effects form the basis of the MAX31782’s higher level op codes,

such as ADDC, OR, and JUMP. While these op codes are actually implemented as MOVE instructions between cer-

tain register locations, the encoding is handled by the assembler and need not be a concern to the programmer. The

unused “empty” locations in the system register modules are used for these higher level op codes.

The instruction set is designed to be highly orthogonal. All arithmetic and logical operations that use two registers can

use any register along with the accumulator. Data can be transferred between any two registers in a single instruction.

2.2 Register Space

The MAX31782 provides a total of 13 register modules broken up into two different groups. These groupings are

descriptive only, as there is no difference between accessing the two register groups from a programming perspective.

The two groups are:

1) Peripheral Registers: These are the lower six modules (Modules 0h through 5h). The peripheral registers in the

MAX31782 are used for functionalities such as ADC, PWM outputs, tachometer inputs, GPIO, etc. The peripheral

registers are not used to implement op codes.

2) System Registers: These are modules 8h, 9h, and Bh through Fh. The system registers in the MAX31782 are used

to implement higher level op codes as well as the following common system features.

• 16-bit ALU and associated status flags (zero, equals, carry, sign, overflow)

• 16 working accumulator registers, each 16-bit, along with associated control registers

• Instruction pointer

• Registers for interrupt control, handling, and identification

• Auto-decrementing loop counters for fast, compact looping

• Two data pointer registers and a frame pointer for data memory access

Each system register module has 16 registers, while each peripheral register module has 32 registers. The number of

cycles required to access a particular register depends upon the register’s index within the module. The access times

based upon the register index are grouped as follows:

• The first eight registers (index 0h to 7h) in each module can be read from or written to in a single cycle.

• The second eight registers (index 8h to 0Fh) can be read from in a single cycle and written to in two cycles (by using

the PFX register).

• The last 16 registers (10h to 1Fh) in peripheral register modules can be read or written in two cycles (always requir-

ing use of the PFX register).

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MAX31782 User’s Guide 1

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