Maxim-integrated High-Speed Microcontroller Users Guide: DS80C390 S Manual de usuario Pagina 86
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High-Speed Microcontroller User’s Guide: DS80C390 Supplement
86 of 158
CAN 1 MESSAGE CENTER 2 CONTROL REGISTER (C1M2C)
7 6 5 4 3 2 1 0
SFR ECh MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
RW-0 RW-0 RW-0 RW-0 RC-0 R*-0 R*-0 R*-0
R = Unrestricted Read, C = Clear Only, * = See description below, -n = Value after Reset
C1M2C
Bits 7-0
Operation of the bits in this register are identical to those found in the CAN 1
Message One Control Register (C1M1C;ABh). Please consult the description
of that register for more information.
CAN 1 MESSAGE CENTER 3 CONTROL REGISTER (C1M3C)
7 6 5 4 3 2 1 0
SFR EDh MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
RW-0 RW-0 RW-0 RW-0 RC-0 R*-0 R*-0 R*-0
R = Unrestricted Read, C = Clear Only, * = See description below, -n = Value after Reset
C1M3C
Bits 7-0
Operation of the bits in this register are identical to those found in the CAN 1
Message One Control Register (C1M1C;ABh). Please consult the description
of that register for more information.
CAN 1 MESSAGE CENTER 4 CONTROL REGISTER (C1M4C)
7 6 5 4 3 2 1 0
SFR EEh MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
RW-0 RW-0 RW-0 RW-0 RC-0 R*-0 R*-0 R*-0
R = Unrestricted Read, C = Clear Only, * = See description below, -n = Value after Reset
C1M4C
Bits 7-0
Operation of the bits in this register are identical to those found in the CAN 1
Message One Control Register (C1M1C;ABh). Please consult the description
of that register for more information.
CAN 1 MESSAGE CENTER 5 CONTROL REGISTER (C1M5C)
7 6 5 4 3 2 1 0
SFR EFh MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
RW-0 RW-0 RW-0 RW-0 RC-0 R*-0 R*-0 R*-0
R = Unrestricted Read, C = Clear Only, * = See description below, -n = Value after Reset
C1M5C
Bits 7-0
Operation of the bits in this register are identical to those found in the CAN 1
Message One Control Register (C1M1C;ABh). Please consult the description
of that register for more information.
- DS80C390 Supplement 1
- 5 of 158 5
- MEMORY MAP 6
- REGISTER MAP 6
- BIT ADDRESSABLE LOCATIONS 6
- WORKING REGISTERS 6
- 7 of 158 7
- 8 of 158 8
- SPECIAL FUNCTION REGISTERS 9
- LSHIFT 10
- PORT 4 (P4) 14
- STACK POINTER (SP) 15
- DATA POINTER LOW 0 (DPL) 15
- DATA POINTER HIGH 0 (DPH) 15
- DATA POINTER LOW 1 (DPL1) 15
- DATA POINTER HIGH 1 (DPH1) 16
- DATA POINTER SELECT (DPS) 16
- POWER CONTROL (PCON) 17
- TIMER/COUNTER CONTROL (TCON) 18
- TIMER MODE CONTROL (TMOD) 19
- TIMER 0 LSB (TL0) 20
- TIMER 1 LSB (TL1) 20
- TIMER 0 MSB (TH0) 20
- TIMER 1 MSB (TH1) 20
- CLOCK CONTROL (CKCON) 21
- PORT 1 (P1) 22
- CE1 CE0 25
- CE2 CE1 CE0 25
- CE3 CE2 CE1 CE0 25
- SERIAL DATA BUFFER 0 (SBUF0) 29
- REVISION ID REGISTER (RID) 29
- ADDRESS PAGE REGISTER (AP) 30
- PORT 2 (P2) 34
- PORT 5 (P5) 34
- CAN 0 CONTROL REGISTER (C0C) 36
- CAN 0 STATUS REGISTER (C0S) 39
- INTERRUPT ENABLE (IE) 44
- 7 6 5 4 3 2 1 0 46
- PORT 3 (P3) 50
- INTERRUPT PRIORITY (IP) 52
- SERIAL PORT CONTROL (SCON1) 55
- SERIAL DATA BUFFER 1 (SBUF1) 56
- STATUS REGISTER (STATUS) 58
- TIMED ACCESS REGISTER (TA) 60
- TIMER 2 CONTROL (T2CON) 61
- TIMER 2 MODE (T2MOD) 62
- TIMER 2 CAPTURE LSB (RCAP2L) 63
- TIMER 2 CAPTURE MSB (RCAP2H) 63
- TIMER 2 LSB (TL2) 63
- TIMER 2 MSB (TH2) 64
- CLOCK OUTPUT REGISTER (COR) 64
- PROGRAM STATUS WORD (PSW) 65
- MULTIPLIER A REGISTER (MA) 68
- MULTIPLIER B REGISTER (B) 68
- MULTIPLIER C REGISTER (C) 69
- WATCHDOG CONTROL (WDCON) 71
- ACCUMULATOR (A or ACC) 74
- CAN 1 CONTROL REGISTER (C1C) 74
- CAN 1 STATUS REGISTER (C1S) 77
- B REGISTER (B) 87
- SYSTEM CLOCK SELECTION 91
- EXTERNAL MEMORY INTERFACING 93
- CE0 CE1 CE2 CE3 94
- START390.A51 file 95
- POWER MANAGEMENT MODES 100
- RESET SOURCES 101
- POWER-ON/FAIL RESET 101
- WATCHDOG TIMER RESET 101
- Reset Output Low (RSTOL) 102
- IN-SYSTEM DISABLE MODE 103
- PORTS 4 AND 5 104
- OUTPUT FUNCTIONS 105
- TIMER/COUNTER 0 AND 1 106
- MODES 0 AND 1 106
- TIMER/COUNTER 2 108
- CLOCK-OUT MODE 108
- (/RL2 = 0) 108
- BAUD RATE GENERATOR MODE 108
- AUTO RELOAD MODE (/RL2 = 0) 109
- DIVIDE-BY-13 OPTION 110
- PROGRAMMABLE CLOCK OUTPUT 110
- DS80C390 111
- 22-BIT PAGED ADDRESSING MODE 114
- MOVX @DPTR, A) 115
- JMP @A+DPTR or the MOVC A 115
- CMA=1, xxxx=4010 121
- MOVX Data 122
- CMA=1, xxxx=4011 123
- MEME MDME 132
- FRAME TYPES 134
- ACK Delimiter 136
- End of Frame 136
- CRC Field ACK Field 136
- CAN INTERRUPTS 139
- INTERRUPT 140
- VECTOR 140
- MESSAGE CENTER 15 141
- Transmitting Data Messages 142
- Receiving Data Messages 142
- Case 1: Automatic Reply 145
- USING THE AUTOBAUD FEATURE 149
- SYNC_SEG 152
- 153 of 158 153
- QUTSEG t)LEN_TS(t 154
- QUSJW t)SJW(t 154
- Threefold Bit Sampling: 155
- Bus Rate Timing Example: 155
- (DS80C390 Supplement Only) 156
- 157 of 158 157
- 40-BIT ACCUMULATOR 158
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