Maxim-integrated 78Q8430 Software Driver Manual de usuario descargar pdf (Pagina 25)

UG_8430_004 78Q8430 Software Driver Development Guidelines

Rev. 1.0 25

5 Media Controller Offload Features

The 78Q8430 has several features that support offloading some IP work from the host processor. This

section describes the following media controller offload procedures:

• Slave DMA Read and Write

• Jumbo frame transmit and receive

• Watermarking

o Headroom Watermark

o PAUSE watermark

o Watermark Interrupt

• Transfer Frame using SNOOP access

o Transmit ARP response

o Transmit ICMP echo reply

• IP Firewall

• IP Checksum Check

• Transmit priority

5.1 DMA

The use of a DMA engine in the host to deliver data to the 78Q8430 is desirable. This allows the transfer

of data to the part with minimal involvement of the central processor. The implementation of a DMA

engine in the host is platform specific. This section describes the 78Q8430 DMA read and write mode

operations.

5.1.1 Slave DMA Read Mode

The 78Q8430 slave DMA mode facilitates the use of various host-side utilities by the driver to read large

blocks of data with improved IO efficiency. Use the following procedure to read a block of data using the

slave DMA read mode:

STEP 1: Set the Read Mode bit and Address field in the DMA register.

The Address field should contain the address of the RDR register for the QUE to be read.

STEP 2: Read the desired amount of data.

Once the slave DMA Read Mode bit is set, all reads on the host interface, regardless of the address

used, read from the programmed RDR indicated by the Address field of the DMA register. The DMA

address is auto-incremented when the host makes successive reads to the RDR.

STEP 3: Write to the DMA register and clear the Read Mode bit to terminate DMA Read Mode.

The Read Mode bit is self-clearing and any write operation on the host interface bus while in slave

DMA read mode terminates DMA mode and clears the bit.

Care must be taken while the 78Q8430 is in DMA mode. If an interrupt service routine is entered

while in DMA mode, the read/write bus operations executed by the interrupt routine may not have

the desired effect. The driver software should consider using a semaphore to the ISR to indicate

the DMA mode to the ISR, or blocking all interrupts, possibly at the HIMR, before entering DMA mode.

5.1.2 Slave DMA Write Mode

Use the following procedure to write a block of data using the slave DMA write mode:

STEP 1: Set the Write Mode bit and Address field in the DMA register.

The Address field should contain the address of the TDR register for the QUE to be written.

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